With the advance in semiconductor technology, feature sizes of complementary metal oxide semiconductor (CMOS) devices can be scaled down to 14 nm technology node and below through incorporating high-k dielectrics in the gate stack, strain engineering techniques, pocket implants and material optimization processes. However, further scaling of planar devices presents a significant challenge due to degrading short channel effects, process variations and reliability degradation.
The technological advance of FinFET devices make it possible to further reduce the feature size of CMOS devices beyond the 14 nm node. Through a fully depleted fin, short channel effect can be controlled, random doping fluctuation can be reduced, parasitic junction capacitance can be reduced, and area efficiency can be improved.
In conventional FinFET manufacturing processes, contacts to the source, drain and gate are formed. However, in the conventional FinFET manufacturing processes, the contacts may be easily electrically connected to each other, thereby adversely affecting the device reliability.
Therefore, there is a need for improved methods of manufacturing a fin-type semiconductor device.